Hydra Subsystem

Hydra SoC consists of:

Ariane

• Linux Capable
• Application class

Each interface has 64 bit Address

• Debug module (64'h0000_0000)
• PLIC (64'h0C00_0000)
• CLINT (64'h0200_0000)

Components are connected through a AXI-CrossBar

Master and Slave Interface

• Present to provide integration between Hydra Subsystem and Xilinx Subsystem

Xilinx Subsystem

Xilinx subsystem performs communication with Hydra Subsystem

Xilinx subsystem contains NOVA's peripherals except DDR

It includes:

• BRAM
• AXI-UART Lite
• AXI Protocol Converter
• Data Width Converter
• Block Memory Controller
• AXI Crossbar